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this product conforms to specifications per the terms of the ramtron ramtron international corporation standard warranty. the product has completed ramtrons internal 1850 ramtr on drive, colorado springs, co 80921 qualification testing and has reached production status . (800) 545 - fram, (719) 481 - 7000 http://www.ramtron.com rev. 3.0 jan. 2012 page 1 of 14 fm 25cl64b 64kb serial 3v f - ram memory features 64k bit ferroelectric nonvolatile ram ? organized as 8,192 x 8 bits ? high endurance 100 trillion (10 14 ) read/writes ? 38 year data retention ( @ +75oc) ? nodelay? writes ? advanced high - re liability ferroelectric process very fast serial peripheral interface - spi ? up to 20 mhz frequency ? direct hardware replacement for eeprom ? spi mode 0 & 3 (cpol, cpha=0,0 & 1,1) sophisticated write protection scheme ? hardware protection ? software protect ion low power consumption ? low voltage operation 2.7 - 3.65v ? 200 ? a active current (1 mhz) ? 3 ? a (typ.) standby current industry standard configuration ? industrial temperature - 40 ? c to +85 ? c ? 8 - pin green/rohs soic and tdfn packages description the fm 25cl 64b is a 64 - kilobit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f - ram is nonvolatile and performs reads and writes like a ram. it provides reliable data retention for 38 years while eliminating th e complexities, overhead, and system level reliability problems caused by eeprom and other nonvolatile memories. t he fm 25cl64b performs write operations at bus speed. no write delays are incurred. data is written to the m emory array immediately after eac h byte has been successfully transferred to the device. the next bu s cycle may commence immediately without the need for data polling . in addition, the product offers substantial write endurance compared with other nonvolatile memories. the FM25CL64B is ca pable of supporting 10 14 read/write cycles, or 100 million times more write cycles than eeprom . these capabilities make the fm 25cl64b ideal for nonvolatile memory applications requiring frequent or rapid writes. examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of eeprom can cause data loss. the fm 25cl64b provides substantial benefits to users of serial eeprom as a hardware drop - in replacement. the fm 25cl64b uses the high - speed spi bus, which enhances the high - speed write capability of f - ram technology. device specifications are guaranteed over an industrial temper ature range of - 40c to +85c. pin configuration pin name funct ion /cs chip select /wp write protect /hold hold sck serial clock si serial data input so serial data output vdd supply voltage vss ground ordering information FM25CL64B - g green 8 - pin soic FM25CL64B - gtr green 8 - pin soic, tape & reel fm25c l64b - dg green/rohs 8 - pin tdfn FM25CL64B - dgtr green/rohs 8 - pin tdfn, tape & reel /cs so /wp vss vdd /hold sck si 8 7 6 5 1 2 3 4 top view cs so wp vss vdd hold sck si 1 2 3 4 8 7 6 5
FM25CL64B - 64kb 3v spi f - ram rev. 3.0 jan. 2012 page 2 of 14 figure 1. block diagram pin descriptions pin name i/o description /cs input chip select: this active low input activates the device. when high, the device enters low - power standby mode, ignores other inputs, and all outputs are tri - stated. when low, the device internally activates the sck signal. a falling edge on /cs must occur prior to every op - code. sck input serial clock: all i/o activity is synchronized to the serial clock. inputs are latched on the rising edge and outputs occur on the falling edge. since the device is static, the clock frequency may be any value between 0 and 20 mhz and may be interrupted at any time. /hold in put hold: the /hold pin is used when the host cpu must interrupt a memory operation for another task. when /hold is low, the current operation is suspended. the device ignores any transition on sck or /cs. all transitions on /hold must occur while sck is l ow. /wp input write protect: this active low pin prevents write operations to the status register . this is critical since other write protection features are controlled through the status register . a complete explanation of write prot ection is provided on pages 6 & 7. si input serial input: all data is input to the device on this pin. the pin is sampled on the rising edge of sck and is ignored at other times. it should always be driven to a valid logic level to meet idd specifications. * si may be co nnected to so for a single pin data interface. so output serial output: this is the data output pin. it is driven during a read and remains tri - stated at all other times including when /hold is low. data transitions are driven on the falling edge of the serial clock. * so may be connected to si for a single pin data interface. vdd supply power supply ( 2.7 v to 3.65v) vss supply ground instruction decode clock generator control logic write protect instruction register address register counter 1 , 024 x 64 fram array 13 data i / o register 8 nonvolatile status register 3 wp cs hold sck so si
FM25CL64B - 64kb 3v spi f - ram rev. 3.0 jan. 2012 page 3 of 14 overview the fm 25cl64b is a serial f - ram memory. the memory array is logically organized as 8,192 x 8 and is accessed using an industry standard serial peripheral interface or spi bus. functional operation of the f - ram is similar to serial eeproms. the major difference between the fm 25cl64b and a serial eeprom with the same pinout is the f - ram s superior write performanc e. memory architecture when accessing the fm 25cl64b , the user addresses 8,192 locations of 8 data bits each. these data bits are shifted serially. the addresses are accessed using the spi protocol, which includes a chip select (to permit multiple devices on the bus), an op - code, and a two - byte address. the upper 3 bits of the address range are dont care values. the complete address of 13 - bits specifies each byte address uniquely. most functions of the fm 25cl64b either are controlled by the spi interfa ce or are handled automatically by on - board circuitry. the access time for memory operation is essentially zero, beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the spi bus. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. so, by the time a new bus transaction can be shifted into the device, a write operation will be complete. this is explained in more detail in the interface section. user s expect several obvious system benefits from the fm 25cl64b due to its fast write cycle and high endurance as compared with eeprom. in addition there are less obvious benefits as well. for example in a high noise environment, the fast - write operation is le ss susceptible to corruption than an eeprom since it is completed quickly. by contrast, an eeprom requiring milliseconds to write is vulnerable to noise during much of the cycle. note : t he fm 25cl64b contains no power management circuits other than a simp le internal power - on reset circuit . it is the users responsibility to ensure that v dd is within datasheet tolerances to prevent incorrect operation. it is recommended that the part is not powered down with chip enable active. serial peripheral interface C spi bus the fm 25cl64b employs a serial peripheral interface (spi) bus. it is specified to operate at speeds up to 20 mhz. this high - speed serial bus provides high performance serial communication to a host microcontroller. many common microcontrollers ha ve hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. the fm 25cl64b operates in spi mode 0 and 3. the spi interface uses a total of four pins: clock, data - in, data - out, and chip select. a typical system configuration uses one or more fm 25cl64b devices with a microcontroller that has a dedicated spi port, as figure 2 illustrates. note that the clock, data - in, and data - out pins are common among all devices. the ch ip select and hold pins must be driven separately for each fm 25cl64b device. for a microcontroller that has no dedicated spi bus, a general purpose port may be used. to reduce hardware resources on the controller, it is possible to connect the two data p ins (si, so) together and tie off (high) the /hold pin. figure 3 shows a configuration that uses only three pins. protocol overview the spi interface is a synchronous serial interface using clock and data pins. it is intended to support multiple devices on the bus. each device is activated using a chip select. once chip select is activated by the bus master, the fm 25cl64b will begin monitoring the clock and data lines. the relationship between the falling edge of /cs, the clock and data is dictated by the s pi mode. the device will make a determination of the spi mode on the falling edge of each chip select. while there are four suc h modes, the fm 25cl64b supports m odes 0 and 3. figure 4 shows the req uired signal relationships for m odes 0 and 3. for both mod es, data is clocked into the fm 25cl64b on the rising edge of sck and data is expected on the first rising edge after /cs goes active. if the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising e dge. the spi protocol is controlled by op - codes. these op - codes specify the commands to the device. after /cs is activated the first byte transferred from the bus master is the op - code. following the op - code, any addresses and data are then transferred. note that the wren and wrdi op - codes are commands with no subsequent data transfer. important: t he /cs pin must go inactive after an operation is complete and before a new op - code can be issued. there is one valid op - code only per active chip select.
FM25CL64B - 64kb 3v spi f - ram rev. 3.0 jan. 2012 page 4 of 14 figure 2. system configuration with spi port figure 3. system configuration without spi port spi mode 0: cpol=0, cpha=0 spi mode 3: cpol=1, cpha=1 figure 4. spi modes 0 & 3 s p i m i c r o c o n t r o l l e r f m 2 5 c l 6 4 b s o s i s c k c s h o l d f m 2 5 c l 6 4 b s o s i s c k c s h o l d s c k m o s i m i s o s s 1 s s 2 h o l d 1 h o l d 2 m o s i : m a s t e r o u t s l a v e i n m i s o : m a s t e r i n s l a v e o u t s s : s l a v e s e l e c t m i c r o c o n t r o l l e r f m 2 5 c l 6 4 b s o s i s c k c s h o l d p 1 . 0 p 1 . 1 p 1 . 2 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
FM25CL64B - 64kb 3v spi f - ram rev. 3 .0 jan. 2012 page 5 of 14 data transfer all data transfers to and from the fm 25cl64b occur in 8 - bit groups. they are synchronized to the clock signal (sck), and they transfer most significant bit (msb) first. serial inputs are registered on the ri sing edge of sck. outputs are driven from the falling edge of sck. command structure there are six commands called op - codes that can be issued by the bus master to the fm 25cl64b . they are listed in the table below. these op - codes control the functions p erformed by the memory. they can be divided into three categories. first, there are commands that have no subsequent operations. they perform a single function such as to enable a write operation. second are commands followed by one byte, either in or out. they operate on the status register . the third group includes commands for memory transactions followed by address and one or more bytes of data. table 1. op - code commands name description op - code wren set write enable latch 0000 0110b wrdi write disa ble 0000 0100b rdsr read status register 0000 0101b wrsr write status register 0000 0001b read read memory data 0000 0011b write write memory data 0000 0010b wren - set write enable latch the fm 25cl64b will power up with writes disabled. the wren c ommand must be issued prior to any write operation. sending the wren op - code will allow the user to issue subsequent op - codes for write operations. these include writing the status register (wrsr) and writing the memory (write). sending the wren op - code causes the internal write enable latch to be set. a flag bit in the status register, called wel, indicates the state of the latch. wel=1 indicates that writes are permitted. attempting to write the wel bit in the status register has no effect on the state of this bit C only the wren op - code can set this bit. the wel bit will be automatically cleared on the rising edge of /s following a wrdi, a wrsr, or a write operation. this prevents further writes to the status register or the f - ram array without another wren command. figure 5 below illustrates the wren command bus configuration. wrdi - write disable the wrdi command disables all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the s tatus register and verifying that wel=0. figure 6 illustrates the wrdi command bus configuration. figure 5. wren bus configuration figure 6. wrdi bus configuration
FM25CL64B - 64kb 3v spi f - ram rev. 3 .0 jan. 2012 page 6 of 14 rdsr - read status register the rdsr comm and allows the bus master to verify the contents of the status register . reading status provides information about the current state of the write protection features. following the rdsr op - code, the fm 25cl64b will return one byte with the contents of the s tatus register . the status register is described in detail in a later section. wrsr C write status register the wrsr command allows the user to select certain write protection features by writing a byte to the status register . prior to issuing a wrsr com mand, the /wp pin must be high or inactive. note that on the fm 25cl64b , /wp only prevents writing to the status register , not the memory array. prior to sending the wrsr command, the user must send a wren command to enable writes. note that executing a wrs r command is a write operation and therefore clears the write enable latch. figure 7. rdsr bus configuration figure 8. wrsr bus configuration (wren not shown) status register & write protection t he write protection features of the fm 25cl64b are multi - tiered. first, a wren op - code must be issued prior to any write operation. assuming that writes are enabled using wren, writes to memory are controlled by the status register . as described above, writ es to the status register are performed using the wrsr command and subject to the /wp pin. the status register is organized as follows. table 2. status register bit 7 6 5 4 3 2 1 0 name wpen 0 0 0 bp1 bp0 wel 0 bits 0 and 4 - 6 are fixed at 0 and can not be modified. note that bit 0 ( ready in eeproms) is unnecessary as the f - ram writes in real - time and is never busy. the wpen, bp1 and bp0 control write protection features. they are nonvolatile (shaded yellow). the wel flag indicates the st ate of the writ e enable latch. attempting to directly write the wel bit in the status register has no effect on its state . this bit is internally set and cleared via the wren and wrdi commands, respectively. bp1 and bp0 are memory block write protection bits. they spec ify po rtions of memory that are write - protected as shown in the following table. table 3. block memory write protection bp1 bp0 protected address range 0 0 none 0 1 1800h to 1fffh (upper ?) 1 0 1000h to 1fffh (upper ?) 1 1 0000h to 1fffh (all)
FM25CL64B - 64kb 3v spi f - ram rev. 3.0 jan. 2012 page 7 of 14 the bp1 and bp0 bits and the write enable latch are the only mechanisms that protect the memory from writes. the remaining write protection features protect inadvertent changes to the block protect bits. the wpen bit controls the effect of the hardware /wp p in. when wpen is low, the /wp pin is ignored. when wpen is high, the /wp pin controls write access to the status register . thus the status register is write protected if wpen=1 and /wp=0. this scheme provides a write protection mechanism, which can preve nt software from writing the memory under any circumstances. this occurs if the bp1 and bp0 are set to 1, the wpen bit is set to 1, and /wp is set to 0. this occurs because the block protect bits prevent writing memory and the /wp signal in hardware preve nts altering the block protect bits (if wpen is high). therefore in this condition, hardware must be involved in allowing a write operation. the following table summarizes the write protection conditions. table 4. write protection wel wpen /wp protected blocks unprotected blocks status register 0 x x protected protected protected 1 0 x protected unprotected unprotected 1 1 0 protected unprotected protected 1 1 1 protected unprotected unprotected memory operation the spi interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the f - ram technology. unlike spi - bus eeproms, the fm 25cl64b can perform sequential writes at bus speed. no page register is needed and any number of sequential writes may be per formed. write operation all writes to the memory begin with a wren op - code with /cs being asserted and deasserted. the next op - code is write. the write op - code is follow ed by a two - byte address value. the upper 3 - bits of the address are ignored. in total , the 13 - bits specify the address of the first data byte of the write operation. this is the starting address of the first data byte of the write operation. subsequent bytes are data bytes, which are written sequentially. addresses are incremented internal ly as long as the bus master continues to issue clocks and keeps /cs low. if the last address of 1fffh is reached, the counter will roll over to 0000h. data is written msb first. the rising edge of /cs terminates a write operation. a write operation is sho wn in figure 9. eeproms use page buffers to increase their write throughput. this compensates for the technologys inherently slow write operations. f - ram memories do not have page buffers because each byte is written to the f - ram array immediately afte r it is clocked in (after the 8 th clock). this allows any number of bytes to be written without page buffer delays. read operation after the falling edge of /cs, the bus master can issue a read op - code. following the read command is a two - byte address va lue. the upper 3 - bits of the address are ignored. in total, the 13 - bits specify the address of the first byte of the read operation. this is the starting address of the first byte of the read operation. after the op - code and address are issued, the device drives out the read data on the next 8 clocks. the si input is ignored during read data bytes. subsequent bytes are data bytes, which are read out sequentially. addresses are incremented internally as long as the bus master continues to issue clocks and / cs is low. if the last address of 1fffh is reached, the counter will roll over to 0000h. data is read msb first. the rising edge of /cs terminates a read operation. a read operation is shown in figure 10. hold the /hold pin can be used to interrupt a se rial operation without aborting it. if the bus master pulls the /hold pin low while sck is low, the current operation will pause. taking the /hold pin high while sck is low will resume an operation. the transitions of /hold must occur while sck is low, but the sck pin can toggle during a hold state.
FM25CL64B - 64kb 3v spi f - ram rev. 3.0 jan. 2012 page 8 of 14 figure 9. memory write (wren not shown) figure 10. memory read endurance the FM25CL64B devices are capable of being accessed at least 10 14 times, rea ds or writes. an f - ram memory operates with a read and restore mechanism. therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. the f - ram architecture is based on an array of rows and columns. rows are defined by a12 - a3 and column addresses by a2 - a0. see block diagram (pg 2) which shows the array as 1k rows of 64 - bits each. the entire row is internally accessed once whether a single byte or all eight bytes are read or written. each byte in the row is counted only once in an endurance calculation. the table below shows endurance calculations for 64 - byte repeating loop, which includes an op - code, a starting address, and a sequential 64 - byte data stream. this causes each byte to experience one endurance c ycle through the loop. f - ram read and write endurance is virtually unlimited even at 20mhz clock rate . table 5. time to reach endurance limit for repeating 64 - byte loop sck freq (mhz) endurance cycles/sec. endurance cycles/year years to reach limit 2 0 37,31 0 1.18 x 10 12 85.1 10 18,660 5.88 x 10 1 1 170.2 5 9,33 0 2.94 x 10 1 1 340.3 0 1 2 3 4 5 6 7 0 1 2 3 4 5 3 4 5 6 7 0 1 2 3 4 5 6 7 o p - c o d e 0 0 0 0 0 0 1 0 m s b 1 3 - b i t a d d r e s s x x x 1 2 1 1 1 0 4 3 2 1 0 7 6 5 4 3 2 1 0 l s b m s b l s b c s s c k s i s o d a t a 0 1 2 3 4 5 6 7 0 1 2 3 4 5 3 4 5 6 7 0 1 2 3 4 5 6 7 o p - c o d e 0 0 0 0 0 0 1 m s b 1 3 - b i t a d d r e s s x x x 1 2 1 1 1 0 4 3 2 1 0 7 6 5 4 3 2 1 0 l s b m s b l s b c s s c k s i s o d a t a 1
FM25CL64B - 64kb 3v spi f - ram rev. 3.0 jan. 2012 page 9 of 14 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to +5.0v v in voltage on any pin with res pect to v ss - 1.0v to +5.0v and v in < v dd +1.0v t stg storage temperature - 55 ? c to + 12 5 ? c t lead lead temperature (soldering, 10 seconds) 26 0 ? c v esd electrostatic discharge voltage - human body model (aec - q100 - 002 rev. e) - charged device model (aec - q100 - 011 rev. b) - machine model ( a ec - q100 - 003 rev. e ) 4kv 1.25kv 300v package moisture sensitivity level msl - 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and t he functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabil ity. dc operating conditions ( t a = - 40 ? c to + 85 ? c, v dd = 2.7 v to 3.65v unless otherwise specified) symbol parameter min typ max units notes v dd power supply voltage 2.7 3.3 3.65 v i dd vdd supply current @ sck = 1.0 mhz @ sck = 20.0 mhz - - 0.2 3.0 ma ma 1 i sb standby current - 3 6 ? a 2 i li input leakage current - ? 1 ? a 3 i lo output leakage current - ? 1 ? a 3 v ih input high voltage 0.7 v dd v dd + 0.3 v v il input low voltage - 0.3 0.3 v dd v v oh output high voltage @ i oh = - 2 ma v dd C 0.8 - v v ol output low voltage @ i ol = 2 ma - 0.4 v v hys input hysteresis 0.05 v dd - v 4 notes 1. sck toggling between v dd - 0.3v and v ss , other inputs v ss or v dd - 0.3v. 2. sck = si = /cs=v dd . all inputs v ss or v dd . 3. v ss ? v in ? v dd and v ss ? v out ? v dd . 4. charac terized but not 100% tested in production. applies only to /cs and sck pins.
FM25CL64B - 64kb 3v spi f - ram rev. 3.0 jan. 2012 page 10 of 14 ac parameters ( t a = - 40 ? c to + 85 ? c , c l = 30pf , v dd = 2.7v to 3.6 5v unless otherwise specified ) symbol parameter min max units notes f ck sck clock frequency 0 20 mhz t ch clock high time 22 ns 1 t cl clock low time 22 ns 1 t csu chip select setup 10 ns t csh chip select hold 10 ns t od output disable time 20 ns 2 t odv output data valid time 20 ns t oh output hold time 0 ns t d deselect time 60 ns t r data in r ise time 50 ns 2,3 t f data in fall time 50 ns 2,3 t su data setup time 5 ns t h data hold time 5 ns t hs /hold setup time 10 ns t hh /hold hold time 10 ns t hz /hold low to hi - z 20 ns 2 t lz /hold high to data active 20 ns 2 notes 1. t ch + t cl = 1/f ck . 2. characterized but not 100% tested in production. 3. rise and fall times measured b etween 10% and 90% of waveform. capacitance ( t a = 25 ? c, f=1.0 mhz, v dd = 3.3v) symbol parameter min max units notes c o output c apacitance (so) - 8 pf 1 c i input c ap acitance - 6 pf 1 notes 1. this parameter is periodically sampled and not 100% tested. ac test conditions input pulse levels 10% and 90% of v dd input rise and fall times 5 ns input and out put timing levels 0.5 v dd output load capacitance 30 pf data reten tion symbol parameter min max units notes t dr @ +85oc 10 - years @ +80oc 19 - years @ +75oc 38 - years
FM25CL64B - 64kb 3v spi f - ram rev. 3.0 jan. 2012 page 11 of 14 serial data bus timing /hold timing power cycle timing power cycle timing ( t a = - 40 ? c to + 85 ? c , v dd = 2.7v to 3.65v unless otherwise specified ) symbol parameter min max units notes t pu v dd (min) to first access start 1 0 - ms t pd last access complete to v dd (min) 0 - ? s t v r v dd rise time 3 0 - ? s/v 1 t vf v dd fall time 3 0 - ? s/v 1 notes 1. sl ope measured at any point on v dd waveform . c s s c k s i s o 1 / t c k t c l t c h t c s h t o d v t o h t o d t c s u t s u t h t d t r t f v d d m i n t p u v d d c s t v r t p d t v f
FM25CL64B - 64kb 3v spi f - ram rev. 3.0 jan. 2012 page 12 of 14 mechanical drawing 8 - pin soic (jedec ms - 012 variation aa) refer to jedec ms - 012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: x x x xx x x= part number, p= package type ( g=soic ) r=rev code, lllllll= lot code ric=ramtron intl corp, yy=year, ww=work week example: fm 25cl64b , green soic package, year 2010, work week 47 fm 25cl 64 b g a 00002g1 ric10 47 xxx x x xx p r ll llll l ricyyww pin 1 3 . 90 0 . 10 6 . 00 0 . 20 4 . 90 0 . 10 0 . 10 0 . 25 1 . 35 1 . 75 0 . 33 0 . 51 1 . 27 0 . 10 mm 0 . 25 0 . 50 45 ? 0 . 40 1 . 27 0 . 19 0 . 25 0 ? - 8 ? recommended pcb footprint 7 . 70 0 . 65 1 . 27 2 . 00 3 . 70
FM25CL64B - 64kb 3v spi f - ram rev. 3.0 jan. 2012 page 13 of 14 8 - pin tdfn (4.0mm x 4.5mm body, 0.95mm pitch) note: all dimensions in millimeters . the exposed pad should be left floating. tdfn package marking scheme for body size 4.0mm x 4.5mm legend: r=ramtron, g=gr een tdfn package , xxxx=base part number llll= lot code yy=year, ww=work week example: green/rohs tdfn package, fm25l6 4b, lot 0003, year 2011, work week 0 7 r 5l6 4 b 0003 1107 rg xxxx llll yyww pin 1 4 . 0 0 0 . 1 4 . 50 0 . 1 0 . 75 0 . 05 0 . 40 0 . 05 0 . 95 0 . 20 ref . pin 1 id 0 . 0 - 0 . 05 2 . 85 ref 3 . 60 0 . 10 2 . 6 0 0 . 1 0 exposed metal pad should be left floating . 4 . 30 0 . 45 0 . 95 recommended pcb footprint 0 . 60 0 . 30 0 . 1
FM25CL64B - 64kb 3v spi f - ram rev. 3.0 jan. 2012 page 14 of 14 revision history revision date summary 1.0 11/15 /2010 initial r elease 1.1 12/15 /2010 added 4x4.5mm dfn package. fixed endurance section on pg 8. 1.2 2/15 /2011 added esd ratings. updated dfn package marking. changed t pu and t vf timing parameters. 3.0 1/6/2012 changed to production status. changed t vf spec.

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